`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/24/2019 11:01:38 AM
// Design Name: 
// Module Name: counter_60_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module counter_60_tb(
    );
    
    wire CO_tb;
    wire[3:0] TNS_tb;
    wire[3:0] UTS_tb;
    
    reg clk_tb;
    reg CLR_tb;
    
    integer i;
    
    initial
    begin
        CLR_tb <= 0;
        clk_tb <= 0;
        for (i = 0; i < 100; i = i + 1)
        begin
            #100 clk_tb = ~clk_tb;
        end
        CLR_tb = 1;
        #1000;
        CLR_tb = 0;
        forever
        begin
            #100 clk_tb = ~clk_tb;
        end
    end
    
    counter_60_24
        #(.max_num(60))
    counter_60_tb(
        .clk_in(clk_tb),
        .tns(TNS_tb),
        .uts(UTS_tb),
        .CO(CO_tb),
        .CLR(CLR_tb)
    );
    
endmodule
